1. Field of the Invention
The present invention relates to semiconductor integrated circuits and methods for manufacturing the internal dielectric structure thereof. More particularly, the present invention relates to a method for controlled intentional formation of voids in an integrated circuit doped glass dielectric film in order to reduce capacitance between adjacent conductors and thereby enhance the circuit speed capability.
2. Description of Related Art
Semiconductor integrated circuits typically contain several different types of conductors, formed from materials such as aluminum alloy and polysilicon. A dielectric layer is used to separate and insulate the various conductors. Doped glass is commonly used as an integrated circuit dielectric because its melting point can be made significantly lower than that of regular glass or other dielectric materials. Borophosphosilica glass (BPSG) is one exemplary type of doped glass. After deposition over a pattern of polysilicon conductors, for example, a relatively rough BPSG dielectric layer can be put through a high temperature reflow process, usually at about 900.degree. C., which in effect melts the BPSG and thereby smooths its surface. Ordinary glass, however, does not melt until roughly 1400.degree. C., so reflow is more difficult and risks damaging other parts of the integrated circuit structure. The smoother BPSG dielectric layer simplifies subsequent processing steps and improves the reliability of the resultant device. Similar advantages result from the use of other types of doped glass.
As integrated circuit dimensions shrink in response to market demands for increased speed and reduced circuit size, the spaces between adjacent conductors also become smaller. However, adjacent conductors and the intervening dielectric material form a parasitic capacitance which limits the signal speed which the conductors can support. The amount of capacitance depends upon the distance between the adjacent conductors as well as the type of dielectric material separating them. This capacitance represents a significant limitation on integrated circuit speed enhancement and size reduction.
In order to minimize the effect of parasitic capacitance, one can either increase the separation between adjacent conductors or reduce the dielectric constant of the material between them. Since size constraints typically prevent sufficient separation of the conductors, the more desirable and practical approach is to reduce the dielectric constant of the separating material. The best dielectric material is a vacuum, which has a dielectric constant of 1.0. Air is also a very good dielectric, with a constant just slightly higher than that of a vacuum. A typical BPSG material, however, has a significantly higher dielectric constant of about 3.6 to 3.9. One technique which has been used to reduce the dielectric constant of the BPSG film between adjacent conductors is to allow voids to form in the film at appropriate locations. The voids can form during the chemical vapor deposition process, for example, in spaces between conductors. These voids are essentially air or vacuum filled and therefore constitute a low dielectric constant region between conductors. In this manner, the capacitance between adjacent conductors is reduced, and the speed performance of the integrated circuit can be improved without increasing device size.
Despite the speed improvements which voids in BPSG films can provide, their proper formation is presently very difficult to control. For example, voids between adjacent conductors are formed when a BPSG layer is deposited on top of a polysilicon conductive pattern. However, during the reflow process, the voids may disappear if the spaces between polysilicon conductors are large enough or the deposited film is thin enough. The voids formed when a BPSG layer about 7000 Angstroms is deposited over a circuit topography of conductors separated by about 1.0 micron are typically eliminated during reflow. It is not possible to forego the reflow process without losing the smoothness and related benefits which that process provides. Therefore, under current practice desirable properly placed BPSG voids are removed by the equally desirable reflow process.
Furthermore, the problem is not solved by simply increasing the thickness of the deposited BPSG film because the resultant voids may be improperly placed and create device yield and reliability problems. For example, voids may form close to the upper surface of the deposited BPSG film. In subsequent processing, it is common for the BPSG film to undergo etching after which a layer of aluminum is deposited from which additional conductors will be formed. If the BPSG is etched down to the level of a void, the void becomes an imperfection in the etched BPSG surface. The imperfection will run parallel to the underlying conductors between which it was formed. When the deposited aluminum layer is etched to form conductors, a portion of the aluminum filling the imperfection may remain and short out the etched conductors. Other problems can result from voids inducing imperfections elsewhere in the circuit structure. As a result, it would usually be better to completely eliminate void formation than to risk imperfections in the BPSG film. In order to obtain the speed advantages of the voids it is therefore essential that void formation be accurately controlled to ensure proper placement in the BPSG layer.
As is apparent from the above, there presently is a need for a method for controlled formation of voids in integrated circuit doped glass dielectric films. The method should permit formation of voids at desired points in the integrated circuit doped glass dielectric in order to obtain significant reductions in capacitance and resultant improvements in circuit speed. The method should also preserve the smoothness and associated benefits provided by the current doped glass reflow process, without risking potential imperfections in subsequent doped glass etching. Furthermore, the method should be compatible with existing deposition and reflow equipment.